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Hi.

I have problem using IBERT core. I'm working with Virtex5 device. I want to use three MGTs(X0Y5, X0Y6, X0Y7) in IBERT core. I'm using system clock at 32 MHz and referent clock at 156.25 MHz. Target line rate is 6.25 Gbps. ChipScope detected one IBERT core and prompt message : "The user clock s not running. Cannot write to or read from IBERT core. Please reconnect the user clock and reconfigure the device". I also use IBERT with one and two MGTs with same and lower speeds but I didn't have this problem.

Can anybody tell me why is this happening?

Please help.

Thanks!

I didn't find the right solution from the Internet.

References: https://forums.xilinx.com/t5/Virtex-Family-FPGAs/Problem-with-IBERT/td-p/22178

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