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As soon as the OFDM V15 design is loaded to the FPGA (on Virtex4 FPGA boards v2.2) the voltage regulator U1 is getting very hot and the voltage output (monitored on the MGT_1.2V test point) is quickly dropping from initial 1.2V to ~800mV and then the regulator enters periodic thermal shut-down state (MGT_1.2V output voltage periodically changes between ~800mV and ~200mV).  Once in this periodic thermal shut-down DVDD_3.3V bus starts to have periodic noise of ~70mVpp and the period of 700us.   

This voltage regulator supplies AVCAUXTX/RX to MGTs (Multi-Gigabit Transceivers) MGT_1.2V bus, and after further checking I don't think this MGT_1.2V should directly affect Tri-Mode Eth MAC or other parts of the design, but for some reason this MGT problem seemed to cause for me unsuccessful, and non-repeatable, BER tests with warpnet example

I have added a heat-sink to this U1 1.2V regulator (Digikey PN: 345-1043-ND), and as well I had to use external fan to keep even this heat-sink from over-heating.  Now the voltage on MGT 1.2V test point, still suddenly drops to ~1.1V, as soon as OFDM v15 design is loaded, but at least it seems to stay stable at this value for long time.  After this modification on two WARP 2.2 boards, the warpnet BER application seems to work well and stable (the modification seemed to significantly improve the measured BER performance, and to fix the 'request time-out' problems I was observing in topic

Although the temporary solution with heat-sink and external fan seems to be working OK for now, I think the MGT protectors design should be revised to reduce the power consumption from AVCAUXTX/RX power bus.

To reduce the consumed power, could we use a much slower clock (instead of 100MHz? fpga_0_clk_board_config_sys_clk) to keep the MGT Protectors running? 

 any suggestions..?

Please help.

Thanks!

I didn't find the right solution from the Internet.

References: https://warpproject.org/forums/viewtopic.php?id=861

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